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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">ID_AA64SMFR0_EL1, SME Feature ID Register 0</h1><p>The ID_AA64SMFR0_EL1 characteristics are:</p><h2>Purpose</h2>
        <p>Provides information about the implemented features of the AArch64 Scalable Matrix Extension.</p>

      
        <p>The fields in this register do not follow the standard ID scheme. See <span class="xref">'Alternative ID scheme used for ID_AA64SMFR0_EL1'</span>.</p>
      <h2>Configuration</h2>
        <div class="note"><span class="note-header">Note</span><p>Prior to the introduction of the features described by this register, this register was unnamed and reserved, <span class="arm-defined-word">RES0</span> from EL1, EL2, and EL3.</p></div>
      <h2>Attributes</h2>
        <p>ID_AA64SMFR0_EL1 is a 64-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>63</td><td>62</td><td>61</td><td>60</td><td>59</td><td>58</td><td>57</td><td>56</td><td>55</td><td>54</td><td>53</td><td>52</td><td>51</td><td>50</td><td>49</td><td>48</td><td>47</td><td>46</td><td>45</td><td>44</td><td>43</td><td>42</td><td>41</td><td>40</td><td>39</td><td>38</td><td>37</td><td>36</td><td>35</td><td>34</td><td>33</td><td>32</td></tr></thead><tfoot><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></tfoot><tbody><tr class="firstrow"><td class="lr" colspan="1"><a href="#fieldset_0-63_63">FA64</a></td><td class="lr" colspan="3"><a href="#fieldset_0-62_60">RES0</a></td><td class="lr" colspan="4"><a href="#fieldset_0-59_56-1">SMEver</a></td><td class="lr" colspan="4"><a href="#fieldset_0-55_52">I16I64</a></td><td class="lr" colspan="3"><a href="#fieldset_0-51_49">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-48_48">F64F64</a></td><td class="lr" colspan="4"><a href="#fieldset_0-47_44">I16I32</a></td><td class="lr" colspan="1"><a href="#fieldset_0-43_43">B16B16</a></td><td class="lr" colspan="1"><a href="#fieldset_0-42_42">F16F16</a></td><td class="lr" colspan="2"><a href="#fieldset_0-41_40">RES0</a></td><td class="lr" colspan="4"><a href="#fieldset_0-39_36">I8I32</a></td><td class="lr" colspan="1"><a href="#fieldset_0-35_35">F16F32</a></td><td class="lr" colspan="1"><a href="#fieldset_0-34_34">B16F32</a></td><td class="lr" colspan="1"><a href="#fieldset_0-33_33">BI32I32</a></td><td class="lr" colspan="1"><a href="#fieldset_0-32_32">F32F32</a></td></tr><tr class="firstrow"><td class="lr" colspan="32"><a href="#fieldset_0-31_0">RES0</a></td></tr></tbody></table><h4 id="fieldset_0-63_63">FA64, bit [63]</h4><div class="field">
      <p>Indicates support for execution of the full A64 instruction set when the PE is in Streaming SVE mode. Defined values are:</p>
    <table class="valuetable"><tr><th>FA64</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Only those A64 instructions defined as being legal can be executed in Streaming SVE mode.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>All implemented A64 instructions are legal for execution in Streaming SVE mode, when enabled by <a href="AArch64-smcr_el1.html">SMCR_EL1</a>.FA64, <a href="AArch64-smcr_el2.html">SMCR_EL2</a>.FA64, and <a href="AArch64-smcr_el3.html">SMCR_EL3</a>.FA64.</p>
        </td></tr></table>
      <p>FEAT_SME_FA64 implements the functionality identified by the value <span class="binarynumber">0b1</span>.</p>
    </div><h4 id="fieldset_0-62_60">Bits [62:60]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-59_56-1">SMEver, bits [59:56]<span class="condition"><br/>When ID_AA64PFR1_EL1.SME != 0b0000:
                        </span></h4><div class="field">
      <p>Indicates support for SME instructions when FEAT_SME is implemented. Defined values are:</p>
    <table class="valuetable"><tr><th>SMEver</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>The mandatory SME instructions are implemented.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>As <span class="binarynumber">0b0000</span>, and adds the mandatory SME2 instructions.</p>
        </td></tr><tr><td class="bitfield">0b0010</td><td>
          <p>As <span class="binarynumber">0b0001</span>, and adds the mandatory SME2.1 instructions.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>If FEAT_SME is implemented
and FEAT_SME2 is not implemented,
the only permitted value is <span class="binarynumber">0b0000</span>.</p>
<p>If FEAT_SME2 is implemented
and FEAT_SME2p1 is not implemented,
the only permitted value is <span class="binarynumber">0b0001</span>.</p>
<p>FEAT_SME2p1 implements the functionality identified by <span class="binarynumber">0b0010</span>.</p></div><h4 id="fieldset_0-59_56-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-55_52">I16I64, bits [55:52]</h4><div class="field">
      <p>Indicates SME support for instructions that accumulate into 64-bit integer elements in the ZA array. Defined values are:</p>
    <table class="valuetable"><tr><th>I16I64</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Instructions that accumulate into 64-bit integer elements in the ZA array are not implemented.</p>
        </td></tr><tr><td class="bitfield">0b1111</td><td><p>The variants of the ADDHA, ADDVA, SMOPA, SMOPS, SUMOPA, SUMOPS, UMOPA, UMOPS, USMOPA, and USMOPS instructions that accumulate into 64-bit integer tiles are implemented.</p>
<p>When FEAT_SME2 is implemented, the variants of the ADD, ADDA, SDOT, SMLALL, SMLSLL, SUB, SUBA, SVDOT, UDOT, UMLALL, UMLSLL, and UVDOT instructions that accumulate into 64-bit integer elements in ZA array vectors are implemented.</p></td></tr></table><p>All other values are reserved.</p>
<p>FEAT_SME_I16I64 implements the functionality identified by the value <span class="binarynumber">0b1111</span>.</p>
<p>The only permitted values are <span class="binarynumber">0b0000</span> and <span class="binarynumber">0b1111</span>.</p></div><h4 id="fieldset_0-51_49">Bits [51:49]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-48_48">F64F64, bit [48]</h4><div class="field">
      <p>Indicates SME support for instructions that accumulate into FP64 double-precision floating-point elements in the ZA array. Defined values are:</p>
    <table class="valuetable"><tr><th>F64F64</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Instructions that accumulate into double-precision floating-point elements in the ZA array are not implemented.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td><p>The variants of the FMOPA and FMOPS instructions that accumulate into double-precision tiles are implemented.</p>
<p>When FEAT_SME2 is implemented, the variants of the FADD, FMLA, FMLS, and FSUB instructions that accumulate into double-precision elements in ZA array vectors are implemented.</p></td></tr></table>
      <p>FEAT_SME_F64F64 implements the functionality identified by the value <span class="binarynumber">0b1</span>.</p>
    </div><h4 id="fieldset_0-47_44">I16I32, bits [47:44]</h4><div class="field">
      <p>Indicates SME2 support for instructions that accumulate 16-bit outer products into 32-bit integer tiles. Defined values are:</p>
    <table class="valuetable"><tr><th>I16I32</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Instructions that accumulate 16-bit outer products into 32-bit integer tiles are not implemented.</p>
        </td></tr><tr><td class="bitfield">0b0101</td><td>
          <p>The SMOPA (2-way), SMOPS (2-way), UMOPA (2-way), and UMOPS (2-way) instructions that accumulate 16-bit outer products into 32-bit integer tiles are implemented.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>If FEAT_SME2 is implemented, the only permitted value is <span class="binarynumber">0b0101</span>. Otherwise, the only permitted value is <span class="binarynumber">0b0000</span>.</p></div><h4 id="fieldset_0-43_43">B16B16, bit [43]</h4><div class="field">
      <p>Indicates support for SME2.1 non-widening BFloat16 instructions. Defined values are:</p>
    <table class="valuetable"><tr><th>B16B16</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>SME2.1 non-widening BFloat16 instructions are not implemented.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>SME2.1 BFADD, BFCLAMP, BFMAX, BFMAXNM, BFMIN, BFMINNM, BFMLA, BFMLS, BFMOPA, BFMOPS, and BFSUB instructions with BFloat16 operands and results are implemented.</p>
        </td></tr></table><p>FEAT_SVE_B16B16 implements the functionality identified by <span class="binarynumber">0b1</span>.</p>
<p>This field must indicate the same level of support as <a href="AArch64-id_aa64zfr0_el1.html">ID_AA64ZFR0_EL1</a>.B16B16.</p>
<p>If FEAT_SME2p1 is implemented, the values <span class="binarynumber">0b0</span> and <span class="binarynumber">0b1</span> are permitted.</p>
<p>Otherwise, the only permitted value is <span class="binarynumber">0b0</span>.</p></div><h4 id="fieldset_0-42_42">F16F16, bit [42]</h4><div class="field">
      <p>Indicates support for SME2.1 non-widening half-precision floating-point instructions. Defined values are:</p>
    <table class="valuetable"><tr><th>F16F16</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>SME2.1 half-precision floating-point instructions are not implemented.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td><p>The following SME2.1 floating-point instructions are implemented:</p>
<ul>
<li>FMOPA and FMOPS instructions that accumulate half-precision outer-products into half-precision tiles.
</li><li>Multi-vector FADD, FMLA, FMLS, and FSUB instructions with half-precision operands and results.
</li><li>Multi-vector FCVT and FCVTL instructions that convert half-precision inputs to single-precision results.
</li></ul></td></tr></table><p>FEAT_SME_F16F16 implements the functionality identified by <span class="binarynumber">0b1</span>.</p>
<p>If FEAT_SME2p1 is implemented, the values <span class="binarynumber">0b0</span> and <span class="binarynumber">0b1</span> are permitted.</p>
<p>Otherwise, the only permitted value is <span class="binarynumber">0b0</span>.</p></div><h4 id="fieldset_0-41_40">Bits [41:40]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-39_36">I8I32, bits [39:36]</h4><div class="field">
      <p>Indicates SME support for instructions that accumulate 8-bit integer outer products into 32-bit integer tiles. Defined values are:</p>
    <table class="valuetable"><tr><th>I8I32</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Instructions that accumulate 8-bit outer products into 32-bit tiles are not implemented.</p>
        </td></tr><tr><td class="bitfield">0b1111</td><td>
          <p>The SMOPA, SMOPS, SUMOPA, SUMOPS, UMOPA, UMOPS, USMOPA, and USMOPS instructions that accumulate 8-bit outer products into 32-bit tiles are implemented.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>If FEAT_SME is implemented, the only permitted value is <span class="binarynumber">0b1111</span>.</p></div><h4 id="fieldset_0-35_35">F16F32, bit [35]</h4><div class="field">
      <p>Indicates SME support for instructions that accumulate FP16 half-precision floating-point outer products into FP32 single-precision floating-point tiles. Defined values are:</p>
    <table class="valuetable"><tr><th>F16F32</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Instructions that accumulate half-precision outer products into single-precision tiles are not implemented.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>The FMOPA and FMOPS instructions that accumulate half-precision outer products into single-precision tiles are implemented.</p>
        </td></tr></table>
      <p>If FEAT_SME is implemented, the only permitted value is <span class="binarynumber">0b1</span>.</p>
    </div><h4 id="fieldset_0-34_34">B16F32, bit [34]</h4><div class="field">
      <p>Indicates SME support for instructions that accumulate BFloat16 outer products into FP32 single-precision floating-point tiles. Defined values are:</p>
    <table class="valuetable"><tr><th>B16F32</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Instructions that accumulate BFloat16 outer products into single-precision tiles are not implemented.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>The BFMOPA and BFMOPS instructions that accumulate BFloat16 outer products into single-precision tiles are implemented.</p>
        </td></tr></table>
      <p>If FEAT_SME is implemented, the only permitted value is <span class="binarynumber">0b1</span>.</p>
    </div><h4 id="fieldset_0-33_33">BI32I32, bit [33]</h4><div class="field">
      <p>Indicates SME support for instructions that accumulate thirty-two 1-bit binary outer products into 32-bit integer tiles. Defined values are:</p>
    <table class="valuetable"><tr><th>BI32I32</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Instructions that accumulate 1-bit binary outer products into 32-bit integer tiles are not implemented.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>The BMOPA and BMOPS instructions that accumulate 1-bit binary outer products into 32-bit integer tiles are implemented.</p>
        </td></tr></table>
      <p>If FEAT_SME2 is implemented, the only permitted value is <span class="binarynumber">0b1</span>. Otherwise, the only permitted value is <span class="binarynumber">0b0</span>.</p>
    </div><h4 id="fieldset_0-32_32">F32F32, bit [32]</h4><div class="field">
      <p>Indicates SME support for instructions that accumulate FP32 single-precision floating-point outer products into single-precision floating-point tiles. Defined values are:</p>
    <table class="valuetable"><tr><th>F32F32</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Instructions that accumulate single-precision outer products into single-precision tiles are not implemented.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>The FMOPA and FMOPS instructions that accumulate single-precision outer products into single-precision tiles are implemented.</p>
        </td></tr></table>
      <p>If FEAT_SME is implemented, the only permitted value is <span class="binarynumber">0b1</span>.</p>
    </div><h4 id="fieldset_0-31_0">Bits [31:0]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><div class="access_mechanisms"><h2>Accessing ID_AA64SMFR0_EL1</h2>
        <p>This register is read-only and can be accessed from EL1 and higher.</p>

      
        <p>This register is only accessible from the AArch64 state.</p>
      <p>Accesses to this register use the following encodings in the System register encoding space:</p><h4 class="assembler">MRS &lt;Xt&gt;, ID_AA64SMFR0_EL1</h4><table class="access_instructions"><tr><th>op0</th><th>op1</th><th>CRn</th><th>CRm</th><th>op2</th></tr><tr><td>0b11</td><td>0b000</td><td>0b0000</td><td>0b0100</td><td>0b101</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    if IsFeatureImplemented(FEAT_IDST) then
        if EL2Enabled() &amp;&amp; HCR_EL2.TGE == '1' then
            AArch64.SystemAccessTrap(EL2, 0x18);
        else
            AArch64.SystemAccessTrap(EL1, 0x18);
    else
        UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; (IsFeatureImplemented(FEAT_FGT) || !IsZero(ID_AA64SMFR0_EL1) || boolean IMPLEMENTATION_DEFINED "ID_AA64SMFR0_EL1 trapped by HCR_EL2.TID3") &amp;&amp; HCR_EL2.TID3 == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    else
        X[t, 64] = ID_AA64SMFR0_EL1;
elsif PSTATE.EL == EL2 then
    X[t, 64] = ID_AA64SMFR0_EL1;
elsif PSTATE.EL == EL3 then
    X[t, 64] = ID_AA64SMFR0_EL1;
                </p></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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